Vue d'ensemble
G茅nie 茅lectrique : Trends in technology. CISC vs. RISC architectures. Pipelining. Instruction level parallelism. Data and Control Hazards. Static prediction. Exceptions. Dependencies. Loop level paralleism. Dynamic scheduling, branch prediction. Branch target buffers. Superscalar and N-issue machines. VLIW. ILP techniques. Cache analysis and design. Interleaved and virtual memory. TLB translations and caches.
Terms: Automne 2009, Hiver 2010
Instructors: Vu, Mai (Fall) Tsikhanovich, Alena (Winter)
- (3-1-5)
- Prerequisites: ECSE 322 and ECSE 323
- Tutorials assigned by instructor.